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Refined by: author/creator: Friedman, E.G. remove topic: Clocks remove
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Clock Distribution Networks in 3-D Integrated Systems

Pavlidis, V. F ; Savidis, I ; Friedman, E. G

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, December 2011, Vol.19(12), pp.2256-2266 [Peer Reviewed Journal]

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Clock distribution networks in synchronous digital integrated circuits

Friedman, E Friedman, E (correspondence author)

Proceedings of the IEEE, 0, 2001, Vol.89(5) [Peer Reviewed Journal]

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Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits

Pavlidis, V ; Friedman, E Pavlidis, V (correspondence author)

Proceedings of the IEEE, 0, 2009, Vol.97(1) [Peer Reviewed Journal]

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Sleep switch dual threshold Voltage domino logic with reduced standby leakage current

Kursun, V ; Friedman, E Kursun, V (correspondence author)

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2004, Vol.12(5) [Peer Reviewed Journal]

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Scaling trends of on-chip power distribution noise

Mezhiba, A ; Friedman, E Mezhiba, A (correspondence author)

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2004, Vol.12(4) [Peer Reviewed Journal]

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Clock frequency and latency in synchronous digital systems

Friedman, E ; Mulligan, J Friedman, E (correspondence author)

IEEE Transactions on Signal Processing, Apr. 1991, Vol.39(4), pp.930-934 [Peer Reviewed Journal]

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Design Methodology for Global Resonant H-Tree Clock Distribution Networks

Rosenfeld, J ; Friedman, E Rosenfeld, J (correspondence author)

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Feb. 2007, Vol.15(2), pp.135-148 [Peer Reviewed Journal]

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An RLC interconnect model based on fourier analysis

Chen, Guoqing ; Friedman, E Chen, Guoqing (correspondence author)

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Feb. 2005, Vol.24(2), pp.170-183 [Peer Reviewed Journal]

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9
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Power characteristics of inductive interconnect

El-Moursy, M ; Friedman, E El-Moursy, M (correspondence author)

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Dec. 2004, Vol.12(12), pp.1295-1306 [Peer Reviewed Journal]

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Retiming and clock scheduling for digital circuit optimization

Liu, Xun ; Papaefthymiou, M ; Friedman, E Liu, Xun (correspondence author)

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2002, Vol.21(2) [Peer Reviewed Journal]

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